EP102 is a high speed 6/8-bit LVDS receiver capable of receiving LVDS inputs at 112 Mhz clock rate. The chip supports single link transmission between the host and the flat panel display up to SXGA resolution. The chip converts the LVDS differential inputs into 18/24-bits RGB data outputs and 3 control outputs (Vsync, Hsync & DE). In 18-bit RGB applications, the 6-bit data can be output left or right justified from the 8-bit data output pins.
•Wide operating frequency range: 25 ~112 Mhz pixel rate
•Wide channel skew tolerance: 1/3 bit time
•Selectable left or right justified in 6-bit data output.
•No external components required
•Power Down Mode
•Single Power Supply (3.3V)
•Low profile 56 Lead TSSOP Package (Pb-free)