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EP936C |
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| Overview |
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EP936C is the 3rd generation HDMI (High Definition Multimedia Interface) transmitter with on-chip HDMI/HDCP/CEC controller. The embedded HDMI/HDCP controller with pre-programmed firmware manages HDMI and HDCP automatically. User does not need to develop the complex firmware for HDMI/HDCP management. The embedded CEC controller provides both protocol level interface and high level CEC commands for user to ease implementation of CEC functions in user side. This helps toreduce the burden of the main MCU greatly and also greatly simplifies system and application design.
The chip is compliant with HDMI Rev 1.3b and HDCP Rev 1.2 specifications. The chip converts input video data in RGB or YUV format and audio data in IIS, SPDIF, DSD or HBR format into HDMI differential signals. The chip supports display resolution from 8-bit VGA to 12-bit 1080p (25-225MHz) with a highly flexible interface in a muxed 18-bits mode or non-muxed 36-bit mode input. In both modes,the chip supports single or dual edge clocking. The CEC Controller receives commands from the main
MCU through IIC interface and handles the CEC physical layer service. |
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| Feature |
• On-chip HDMI/HDCP controller which manages HDMI and HDCP automatically. User does not need to develop complex HDMI/HDCP management firmware
• On-chip CEC controller which provides both protocol level interface and high level CEC
commands for user to ease implementation of CEC functions in user side
• Integrated HDCP keys
• HDMI Specification 1.3b and CEC Specification Compliant
• Integrated HDCP encryption engine which is compliant with HDCP Rev 1.2 specification for transmitting protected content
• Wide TMDS Clock Frequency Range: 25MHz - 225MHz
• Support 8-bit, 10-bit and 12-bit Deep Color modes
• Support IIS, SPDIF (LPCM or compressed), DSD (Super Audio CD) and HBR (True HD High Bit
Rate) audio types
• Support auto-send for DVI, ADO, ACR (Audio Clock Regeneration) and General Control packets.
• Support 2 Generic Data Packet buffers
• Flexible Graphic Controller Interface: mixed 18-bit and non-muxed 36-bit mode in RGB or YUV, embedded sync or separate sync
• Support 1 port of SPDIF audio input (without the need for system clock), 4 ports of IIS audio inputs
or 8 channels of DSD audio inputs
• Supports audio down sampling at 1/2, 1/3 or 1/4 sampling rate for both SPDIF and IIS
• Supports CCIR YUV422 format input
• On-chip YUV422 to YUV444 conversion and YUV444 to YUV422 conversion
• On-chip YUV to RGB and RGB to YUB conversion in ITU-R BT.601 and 709 color space
• Support 10-bit to 8-bit Dithering for 8-bit RGB/YCbCr output
• Programmable Single/Dual Edge Clocking Mode
• IIC Slave Programming Interface
• Programmable DE generation
• Supports x2, x4 and x8 Pixel Repetition
• Supports input De-Skewing
• Supports Receiver Hot Plug Detection and Receiver Connection Detection
• Downward compatible with DVI 1.0
• Support Protocol Level CEC services
– Handles CEC message receiving/transmission and signalling
– Handles CEC arbitration
– Handles CEC Flow Control and Frame Re-transmissions
– Handles CEC Frame Validation
– CEC Line Error Detection and Handling.
• Support High Level CEC services
• Supports Standby Mode
• Support Wake-up by CEC and Host from Standby
• 3.3V and 1.8V power required
• 100-Pin LQFP |
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．微驅科技股份有限公司EXPLORE MICROELECTRONICS INC.
新竹市科學工業園區園區二路47號105室 RM 105, No. 47, Park Ave 2, Hsinchu Science Park, Hsin-Chu, Taiwan, R.O.C. TEL：886-3-564-3595 FAX：886-3-564-3596 |
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．益士伯電子股份有限公司Explore Semiconductor, Inc.
台北縣汐止市新台五路一段79號5F之4 5F.-4, No. 79, Sec. 1, Shintai 5th Rd., Shijr City, Taipei, Taiwan, R.O.C. TEL：886-2-26989727 |
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