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EP103
Overview
 
The EP103 LVDS transmitter supports transmission between the host and the flat panel display up to SXGA+ resolutions. The transmitter converts 32 bits (10-bits/color, 2 dummy bits) of CMOS/TTL data and 3 control bits into 5 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 135MHz, each LVDS differential data pair speed is 945Mbps, providing a total throughput of 4.7Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an external pin.
Feature

The EP103 includes the following distinctive features:
•    Support 8MHz to 135MHz clock rates for NTSC to SXGA+ resolution
•    Up to 4.7Gbps bandwidth
•    PLL requires no external components
•    Cycle-to-cycle jitter rejection
•    Programmable data and control strobe select
•    Reduced swing LVDS supported
•    Power down mode supported
•    Compatible with THine THC63LVD103
•    Single 3.3V CMOS design
•    64-pin LQFP (Pb Free, compliant to JEDEC/IPC J-STD-006)

 
  .微驅科技股份有限公司EXPLORE MICROELECTRONICS INC.
新竹市科學工業園區園區二路47號105室 RM 105, No. 47, Park Ave 2, Hsinchu Science Park, Hsin-Chu, Taiwan, R.O.C. TEL:886-3-564-3595 FAX:886-3-564-3596
  .益士伯電子股份有限公司Explore Semiconductor, Inc.
台北縣汐止市新台五路一段79號10F之13 10F.-13, No. 79, Sec. 1, Shintai 5th Rd., Shijr City, Taipei, Taiwan, R.O.C. TEL:886-2-26989727