EP9553(E) 

Part Number:EP9553(E)

Overview

EP9553(E) is a 3-Port Low Power HDMI/MHL/MCU combo receiver which is compliant with HDMI 1.4 and MHL 2.0 specifications. The on-chip HDMI/MHL/CEC/CBUS controller makes the user very easy to use the chip. It manages HDMI/MHL protocol switching automatically without the need for user to develop firmware. The CEC Controller provides the CEC physical layer transceiver and handles the protocol layer automatically. The CBUS Controller provides the translation between the MHL RAP/RCP Request and the HDMI CEC Command automatically. The CBUS Controller also supports the MSC UCP protocol. The chip supports 1 HDMI/MHL dual mode port (Port 1) and 2 MHL ports (Port 0 and Port 2). The chip supports Video Output up to 1080p 60 Hz. The chip also supports 2-channel IIS and S/PDIF Audio Outputs. The chip integrates Equalizer Switches, HDMI/MHL core, HDCP engine and EDID RAM

Features

•On-chip HDMI/MHL controller which manages HDMI and MHL Protocol automatically
•On-chip CEC controller which provides CEC Physical Layer Transceiver and handle the Protocol Layer without the need for user to develop firmware
•On-chip CBUS controller which provides the translation between the MHL RAP/RCP Request and the HDMI CEC Command
•On-chip CBUS controller which provides the MSC UCP Protocol
•On-chip HDMI/MHL Receiver core which is compliant with HDMI 1.4 and MHL 2.0 specifications
•On-chip HDCP Engine which is compliant with HDCP 1.4 specification
•Support 1 HDMI/MHL dual mode port (Port 1) and 2 MHL ports (Port 0 and Port 2)
•Support up to 1080p 60 Hz for HDMI input
•Support up to 75 Mhz Pixel clock rate (8-bit 1080i/720p 60 Hz) in 24-bit mode and up to 150 Mhz Pixel clock rate (8-bit 1080p 60Hz YCC422) in Packed Pixel mode for MHL input
•Supports 24-bit color video output up to 1080p 60 Hz
•On-chip EDID RAM
•On-chip Audio Decoder which support 8-channel IIS/DSD and SPDIF audio outputs
•Supports Standard Audio, DSD Audio and HD (HBR) Audio
•Support audio soft mute
•Support SPDIF Channel Status extraction
•On-chip YCC422 to YCC444 conversion and YCC444 to YCC422 conversion
•On-chip YCC to RGB and RGB to YCC conversion in ITU-R BT.601 and 709 color space
•Support 24-bit RGB or 24-bit YCbCr 4:4:4 or 16-bit YCbCr 4:2:2 digital video output
•Support Bit Sequence Reverse and Port Swapping in video output ports to ease PCB layout
•Support DDR Clock in digital video outputs
•Register-programmable via slave IIC interface
•Flexible interrupt registers with interrupt pin
•Link On and Valid DE Detection
•Controllable tri-state for output ports
•Low stand-by current (< 1mA) at power down mode •128-pin LQFP

Block Diagram