EPF021J
10 6 月, 2019EP91H0
10 6 月, 2019Part Number:EPF035
Overview
EPF035 is a low cost high performance Micro Controller with 128KB embedded Flash, USB 1.1 Host/Device and USB 2.0 switch Function. The chip integrates 80515 core, 128KB embedded Flash, 256 + 4KB RAM, USB 1.1 Host/Device, USB 2.0 Switch, Timer, Watchdog Timer, Serial Port, 9-bit PWM, SPI, SMBUS, Fan Tachometers, PS2, LPC, PECI 3.0, 10-bit ADC, Remote Decoder, Keyboard Interrupt and GPIO in a single chip.
Features
•On-chip 80515 core with 128K bytes Flash, 256 bytes Direct RAM and 4K bytes on-chip auxiliary RAM
•Fast CPU rate (24Mhz). 41.6 ns for shortest instruction
•Programmable CPU clocks from 24 Mhz to 500 Khz
•Programmable crystal start-up cycles from 0 to 4096 cycles
•Supports Idle mode and Stop mode for power saving.
•Supports crystal/CPU wake-up from Stop mode
•Supports In Circuit Flash programming (ICP)
•Supports 24 external interrupts
•Supports keyboard interrupt on 8 GPIO pins.
•On-chip USB Host/Device 1.1 which supports end-pint 0, 1, 2 and 64-byte bulk transfer
•On-chip USB 2.0 Switch Function
•On-chip 4 Timers supporting Timer, Pulse Output, Event Counter and Pulse Width Measurement modes
•On-chip 15-bit programmable Watchdog Timer
•On-chip Serial Port which supports Synchronous mode and 8/9-bit UART modes
•On-chip Serial Peripheral Interface (SPI) supporting both Master and Slave modes
•On-chip 16 channels of 9-bit PWM with programmable repetition rate
•On-chip 8 channels of Fan Tachometers
•On-chip 16 channels of 10-bit ADC
•On-chip 4 SMBUS ports (2 masters and 2 slaves) with configurable pin outs
•On-chip Low Pin Count (LPC) module for host interface
•On-chip 1 channels of hardware PS/2 interface
•On-chip PECI 3.0 module for host interface
•On-chip Consumer Infra-Red Remote Receiver (CIR) which supports NEC and Phillips RC-5/RC-6 protocols
•Support maximum of 103 General Purpose I/O pins. Among them, 1 port (Port 8) supports By-Pass feature. Most of the I/O ports are 5V tolerant.
•Timer, SPI, PS2, LPC, ADC and USB pins can be used as GPO or GPIO if the associated function is not enabled
•On-chip Low Voltage Inhibit (LVI) circuit which provides reliable power up reset and prevent accidental data loss in Flash
•128-pin LQFP package (Pb-Free)